XA6SLX25-2CSG324Q (Muag los ntawm Tshuag nrog thawj ntim)

Cov khoom siv:

General Description:

Xilinx Automotive (XA) Spartan®-6 tsev neeg ntawm FPGAs muab kev sib koom ua ke muaj peev xwm nrog tus nqi qis tshaj plaws rau kev siv tsheb loj.Cov tsev neeg kaum tsev xa cov kev nthuav dav xws li 3,840 txog 101,261 cov logic hlwb thiab nrawm dua, kev sib txuas ntau dua.Ua los ntawm kev paub tab 45 nm tsis tshua muaj hluav taws xob tooj liab txheej txheem thev naus laus zis uas xa cov txiaj ntsig zoo ntawm tus nqi, lub zog, thiab kev ua haujlwm, XA Spartan-6 tsev neeg muaj qhov tshiab, muaj txiaj ntsig zoo dua, dual-sau npe 6-cov tswv yim saib lub rooj (LUT ) logic thiab nplua nuj xaiv ntawm built-in system-theem blocks.Cov no suav nrog 18 Kb (2 x 9 Kb) thaiv RAMs, tiam thib ob DSP48A1 hlais, SDRAM nco controllers, txhim khu kev sib xyaw-mode moos tswj blocks, SelectIO™ thev naus laus zis, lub zog ua kom zoo tshaj plaws high-speed serial transceiver blocks, PCI Express® tau tshaj Endpoint blocks , advanced system-theem kev tswj fais fab hom, pib-nrhiav kev xaiv, thiab txhim kho IP kev ruaj ntseg nrog AES thiab Device DNA tiv thaiv.Cov yam ntxwv no muab cov nqi qis qis rau lwm txoj hauv kev rau ASIC cov khoom lag luam nrog qhov yooj yim ntawm kev siv tsis tau pom dua.XA Spartan-6 FPGAs muab cov kev daws teeb meem zoo tshaj plaws rau kev hloov pauv tau yooj yim thiab ua kom muaj peev xwm ua tau raws cov qauv tsim, siab-bandwidth parallel DSP cov qauv tsim, thiab cov nqi siv hluav taws xob uas yuav tsum muaj ntau yam kev sib tshuam.XA Spartan-6 FPGAs yog lub hauv paus programmable silicon rau Targeted Design Platforms uas xa cov software thiab cov khoom siv sib xyaw ua ke uas ua rau cov neeg tsim qauv tsom mus rau kev tsim kho tshiab sai li sai tau thaum lawv txoj kev loj hlob pib.Summary of XA Spartan-6 FPGA Features • XA Spartan-6 Family: • XA Spartan-6 LX FPGA: Logic optimized • XA Spartan-6 LXT FPGA: High-speed serial connectivity • Automotive Temperatures: • I-Grade: Tj = – 40°C to +100°C • Q-Qib: Tj = –40°C to +125°C • Automotive Standards: • Xilinx is ISO-TS16949 compliant • AEC-Q100 qualification • Production Part Approval Process (PPAP) documentation • Tshaj li AEC-Q100 kev tsim nyog muaj nyob rau ntawm kev thov • Tsim los rau tus nqi qis • Ntau qhov sib xyaw ua ke zoo • Kev xaiv zoo ntawm I/O cov qauv • Staggered pads • High-volume plastic wire-bonded packages • Low static and dynamic power • 45 nm process optimized rau tus nqi thiab tsis muaj zog • Hibernate fais fab-down hom rau xoom fais fab • Suspend hom tswj lub xeev thiab configuration nrog multipin wake-up, tswj kev txhim kho • High performance 1.2V core voltage (LX thiab LXT FPGAs, -2 thiab -3 ceev qib) • Multi-voltage, ntau tus qauv SelectIO interface cov tsev txhab nyiaj • Mus txog 1,080 Mb/s cov ntaub ntawv hloov pauv tus nqi ibQhov sib txawv I/O • xaiv tau tso zis tsav, mus txog 24 mA ib tus pin • 3.3V rau 1.2VI/O cov qauv thiab cov txheej txheem • Tsawg-nqi HSTL thiab SSTL nco interfaces • Kub sib pauv ua raws • Kho I/O slew tus nqi los txhim kho teeb liab kev ncaj ncees • High-speed GTP serial transceivers nyob rau hauv LXT FPGAs • Mus txog 3.2 Gb/s • High-speed interfaces xws li: Serial ATA thiab PCI Express • Ua tau zoo DSP48A1 slices • High-performance arithmetic thiab teeb liab ua • ceev 18 x 18 multiplier thiab 48 -ntsis accumulator • Pipelining thiab cascading muaj peev xwm • Pre-adder los pab lim daim ntaub ntawv • Integrated Memory Controller blocks • DDR, DDR2, DDR3, thiab LPDDR kev them nyiaj yug • Cov ntaub ntawv tus nqi mus txog 800 Mb/s • Multi-chaw nres nkoj qauv nrog FIFO ywj siab rau txo cov teeb meem tsim lub sij hawm • Ntau cov khoom siv logic nrog kev muaj peev xwm nce ntxiv • Kev xaiv hloov pauv hloov pauv lossis faib RAM txhawb nqa • Siv tau 6-cov tswv yim LUTs txhim kho kev ua tau zoo thiab txo qis zog • LUT nrog dual flip-flops rau pipeline centric applications • Thaiv RAM with ib tug ntau yam ntawm granularity • ceev nrooj RAM nrog byte sau enable • 18 Kb blocks uas yuav optionally programmed li ob ywj siab 9 Kb thaiv RAMs • Clock Management Tile (CMT) rau kev txhim kho kev ua tau zoo • Tsis tshua muaj suab nrov, saj zawg zog clocking • Digital Clock Managers (DCMs) tshem tawm lub moos skew thiab lub luag hauj lwm lub voj voog distortion • Phase-Locked Loops (PLLs) rau qis-jitter clocking • Zaus synthesis nrog ib txhij multiplication, faib, thiab theem hloov • kaum rau qis-skew ntiaj teb moos tes hauj lwm • Simplified configuration, txhawb qis- Cov qauv nqi • 2-pin nws pib-nrhiav teeb tsa • Sab nraud SPI (txog x4) thiab NOR flash txhawb • MultiBoot kev txhawb nqa rau cov chaw taws teeb hloov kho nrog ntau cov bitstreams, siv kev tiv thaiv saib xyuas • Txhim kho kev ruaj ntseg rau kev tiv thaiv kev tsim • Cov Ntaus Cim DNA cim rau tsim authentication • AES bitstream encryption nyob rau hauv lub XA6SLX75, XA6SLX75T, thiab XA6SLX100 li • Integrated Endpoint thaiv rau PCI Express designs (LXT) • nqi qis PCI® technology support tau tshaj 33 MHz, 32- thiab 64-ntsis specification.• Kev ua haujlwm nrawm dua nrog kev txhim kho, tus nqi qis, MicroBlaze™ 32-ntsis mos processor • Kev lag luam ua tus IP thiab cov qauv siv • Muaj zog tsheb tshwj xeeb tshwj xeeb thib peb ecosystem nrog IP, kev tsim kho vaj tse, thiab kev pabcuam tsim